In order to realize downsizing, speed-up, sophistication, and so on of a semiconductor device, a semiconductor device with a SiP (System in Package) structure where a plurality of semiconductor chips are stacked and sealed in one package is in practical use. The semiconductor device with the SiP structure has, for example, a wiring board, semiconductor chips such as a memory chip mounted and a controller chip on the wiring board, and a sealing resin layer sealing such semiconductor chips collectively. It is general that a system LSI chip such as a controller chip, whose outer shape is smaller than that of the memory chip, is disposed on a chip stacked body made by stacking memory chips in multistage. In such a case, since a wiring length from the wiring board to the system LSI chip is long, deterioration or the like of a signal transfer rate is concerned.
In order to cope with the above, it is proposed to embed a system LSI chip in an adhesive layer bonding a memory chip to a wiring board. According to such a structure, a semiconductor device can be down-sized and a wiring length from the wiring board to the system LSI chip can be shortened. Therefore, it becomes possible to provide a semiconductor device which is small in size and can cope with a high-speed device. However, in embedding the system LSI chip in the adhesive layer of the memory chip, occurrence of various problems is concerned. For example, there is an apprehension that the memory chip is deformed into a convex shape when the system LSI chip is embedded in the adhesive layer, or that a void is generated due to insufficient embedding of the system LSI chip. A deformation of the memory chip causes an operation failure. The void generated in a circumference of the system LSI chip causes occurrence of a crack or the like.